The presence of DC offset in a data signal can be a significant problem in high speed, high sensitivity, post amplifiers utilized in optical communication systems. In general, two distortion sources can contribute to DC offset in an amplified data signal: (1) the DC offset already present in the input data signal, which may be caused by duty cycle distortion, data pattern irregularities, or practical limitations of the communication system components; and (2) internal DC offset generated by the amplifier circuit itself, which is caused by asymmetry or mismatching of the amplifier devices. When a low level data signal is amplified by a highly sensitive amplifier circuit, even small amounts of DC offset can significantly degrade the quality of the amplified data signal.
The prior art contains several DC offset cancellation techniques that address the problem of DC offset in a processed data signal. Typically, such prior art techniques suffer from one or more of the following shortcomings: (1) limited to the cancellation of “internal” DC offset generated by the amplifier circuit, and not able to cancel “external” DC offset that may be present in the amplifier input signal; (2) the need for off-chip components; (3) high operating power requirements; and (4) limited to relatively low speed operation, e.g., below 1 Gbps (especially for practical CMOS implementations).